BBSIM(1:LOCAL) BBSIM(1:LOCAL)
NAME
bbsim - simulate a bang-bang pll
SYNOPSIS
bbsim [ options ]
DESCRIPTION
bbsim is a program written in C which produces ascii "X Y" time domain
output suitable for driving autoplot(1), or the ap(1) X11 plotting
script. Autoplot is available by anonymous ftp from inside Agilent
at yaz.labs.agilent.com:pub/autoplot.shar. Alternatively, data can be
plotted by tools such as gnuplot or Rlab.
OPTIONS
-? (print a usage message).
-a <input phase mod amplitude>
This option allows testing the loop with sinusoidal phase
modulation with amplitude specified in units of BB times. The
-f option sets the frequency. Default phase modulation is 0.
-b <bangbang time>
The standard loop has all parameters normalized to BB time =
1. This option allows changing the default BB time for
comparison purposes.
-e (plot phase error rather than phase)
The simulator normally plots data input phase along with loop
tracking phase. For examining eye margin, the -e option will
show the tracking error instead.
-f <input phase mod period (normalized to update times)>
Although this option is -f (making one think of "frequency"),
it actually specifies the modulation period in update times.
For instance a 2.5Gb/s link has an update time of 400ps. A 1
MHz phase modulation on the input waveform would be 1us/400ps
= 2500 update times. This could be simulated with "-f 2500".
-i <number of interpolated points per timestep>
The simulator normally outputs the VCO phase only at the
sampling instant. The -i option will generate n interpolated
values between sampling instants. This is useful to show the
quadratic curvature of the loop response between sampling
points.
-j <gaussian data input jitter (rms)>
This option adds gaussian jitter to the input waveform. The
jitter sigma is specified as a multiple of the BB time.
Random jitter can be used in conjunction with the -f and -a
options. The default jitter is 1 BB unit RMS.
-l <phase detector latency (in bit-times)>
This option allows simulating pipeline delay in the phase
detector logic.
-m <vco mismatch normalized to bb>
When the -m option is specified, the -p (stability) parameter
is ignored, and a first order loop is simulated (no charge
pump). The -m option specifies a VCO mismatch from nominal
frequency in units of BB delta F.
-n <number of timesteps to simulate>
-o <vco starting phase (in bb units)>
This option allows simulation of phase acquisition with an
initial phase step.
-p <stability factor psi>
This option specifies the ratio of the linear phase change to
the quadratic phase change during one update time. A first
order loop is the limit as psi goes to infinity. According to
one way of analyzing the loop, this is equal to
(2*Beta*Tau/tupdate).
-q <normalized cycle-to-cycle sigma> (simulate oscillator phase noise)
The delay of each gate in a ring oscillator is well modelled
by (tau + sigma). After N such delays, the timing of the Nth
VCO clock edge is N*tau + sqrt(sigma). The -q option adds an
integrated noise to the incoming signal. In other words, the
random value at the Nth update time is the next term in an
ongoing summation of N random gaussian variates with the
specified cycle-to-cycle sigma (normalized to bb delta T).
The default VCO jitter is 0 BB unit RMS.
-r (plot data phase also)
Normally, just the loop phase is plotted. This option plots
the data phase also.
-s (statistics only)
all waveform output is inhibited and a summary of loop
statistics is printed instead. The format looks like: "STAT:
1 3 3 0.996019 2.7426" where the fields are
specified_jitter_value, psi, max_pd_hi, max_pd_lo,
actual_sigma_data_jitter, actual_sigma_vco_jitter. The pd
hi/lo counts can be used to estimate when the loop goes into
slew-rate limiting.
-t (output tplot title)
This flag turns on autoplots-style x and y axis labels plus a
title showing the command line options.
-v (verbose flag)
This option is parsed but currently does nothing. It is
reserved for debugging and custom modification of the source
code.
-w (do windowed dft freq & gain calc.)
When used with -f and -a, the -w option performs a windowed
DFT frequency and phase calculation to measure jitter transfer
gain. The DFT uses data from the second half of the
simulation time interval and uses a triangular window to
minimize truncation effects. The output format looks like:
DFT: period input_amplitude output_amplitude output_phase
-x <transition probability>
This option controls transition probability of the data. The
default is "-x 1" which simulates "1010..." data with a
transition at every bit boundary. Specifying "-x 0.5" is a
good simulation of random or scrambled data. Using integer -x
values greater than one will simulate deterministic data
patterns of various runlengths. For example, -x 5, will
simulate the loop with a data pattern of
"00000111110000011111...".
-z (tristate during non-transition times)
This option turns tristating on/off. The default is off.
EXAMPLES
To simulate a bb loop for 1000 time steps with stability of 20, random
transition density of .3 and an input random jitter of 2 bb units
(rms):
bbsim -n 1000 -p 20 -x .3 -j 2 | ap
Notice that VCO phase noise affects the loop the same as input phase
noise (both need to be tracked and "use up" part of the loop jitter
tolerance capability). Here's the same simulation as the previous
example, but with a VCO exhibiting a random jitter sigma of 0.1 bb
units (rms) in addition to the random input data jitter of 2 bb units
(rms):
bbsim -n 1000 -p 20 -x .3 -j 2 -q 0.1 | ap
Same as above with autoplot titles and showing the input phase
waveform as a separate trace:
bbsim -n 1000 -p 20 -x .3 -j 2 -t -r | ap
Same as above, but looking at a phase aquisition transient starting
500 bb units out of lock:
bbsim -n 1000 -p 20 -x .3 -j 2 -t -r -o 500 | ap
The same loop, but tracking a phase modulated input with a pk/pk
amplitude of 10 bb phase units, and a period of 500 update times:
bbsim -a 10 -f 500 -n 1000 -p 20 -x .3 -j 2 -t -r | ap
An ideal loop, with no input jitter whatsoever:
bbsim -x.5 -n 1000 -p 20 -j 0 -t -r | ap
The same loop with tristating. Notice the big reduction in hunting
jitter during long runlengths:
bbsim -z -x.5 -n 1000 -p 20 -j 0 -t -r | ap
FILES
A paper describing the theoretical foundations of the simulator
is Walker, R.C., Designing Bang-bang PLLs for Clock and Data
Recovery in Serial Data Transmission Systems, pp. 34-45, a chapter
appearing in "Phase-Locking in High-Performance Sytems - From
Devices to Architectures", edited by Behzad Razavi, IEEE Press,
2003, ISBN 0-471-44727-7. An electronic copy should be available
at http://www.omnisterra.com/walker/pubs.html.
AUTHOR
Rick Walker (rick_walker@www.omnisterra.com)