(click on image for larger view)
The green trace is the simulated data jitter, and the red trace
is the loop phase trajectory which is attempting to track the
data.
A general purpose bb loop simulator was written to numerically simulate a BB loops with various non-idealities.
The program is written in C and runs under UNIX, producing time domain output suitable for driving a plotting package. A description of the program is available here and the C source is here. .
A paper describing the theoretical foundations of the simulator is Walker, R.C., Designing Bang-bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems , pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7.
A "traditional" BB loop requires both an integral and proportional loop control to manage the very wide tuning range of an on-chip VCO.
The charge pump required for proportional control is expensive, needing 4 bond pads plus an external capacitor.
To economically allow multiple channels on a high-speed transceiver, several authors have used only one charge pump per chip. For a multiple transceiver, it is possible to use only one second-order TX PLL, and to use first-order PLLs for all the RX channels. The RX PLLs may be run with proportional (BB) only if their VCO center frequency can be held accurate to a fraction of the BB-deltaF by using a replica of the TX tune voltage.
Here is an example 1.25G Quad receiver, with a measured BB delta T of 11 ps. This corresponds to a BB delta F of (11p/800p)*1.25GHz = 11 MHz. We simulate a VCO frequency error of 4 MHz. This is a VCO mismatch of 36% BB delta F.
Here is this loop simulated with 100% transition density and no-tristate:
Same loop with "1111100000" data.
Notice that the peak/peak jitter is about 5x the first simulation. This is a characteristic problem of a non-tristated loop with long run lengths.
Now lets look at the performance with tristating. First with 100% transition density:
And then with "1111100000" data.
The complete loss of lock here is caused by the steady state vco mismatch. When the runlength is 5, the effective VCO BB delta F is 20% of normal. This is insufficient to track out the 25% VCO mismatch relative to BB delta F. The next plot shows a VCO mismatch of 19%, which will just be within the 20% allowed by the run-length.
The resulting loop is stable, but has a very tiny slew rate in the vertical direction (20%-19% = 1% of BB delta T/update time). This causes the funny behavior that the loop tracks to outer edge of the input jitter. This is because a very slowly approaching edge will be repelled by very rare excursions before it ever gets to the center of the distribution.
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